The opportunity
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models.
What you'll do
Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation.
Extend and integrate hardware compiler stacks (frontends, IR passes,: lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows.
Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure.
Work closely with designers and verification engineers to turn real pain points into durable tools.
Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability.
Be willing to go all the way down the stack when necessary, including: gate-level views, synthesis results, and implementation artifacts.
What they're looking for
- Help enable PPA optimization loops by building analysis and automation around: area, timing, and power tradeoffs, and by improving tooling that impacts those outcomes.
- Demonstrated ability to build and maintain software (projects, internships,: research, open source, or equivalent experience).
- Strong CS fundamentals: data structures, algorithms, debugging, and software design.
- Proficiency in at least one of Rust, C++, or Python (and willingness to learn the rest).
