The opportunity
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
What you'll do
Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex: SoCs and participate in integration tasks using Verilog/SystemVerilog
Participate in the full ASIC/FPGA design lifecycle for Starlink projects,: from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
Engage in high-level architectural design for FPGA and ASICs
Collaborate with cross-functional engineers in developing new technologies: for the Starlink program impacting User terminals, Satellites, and more
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
What they're looking for
- Master’s in Electrical/Computer Engineering or related field
- ASIC/FPGA system integration experience
- Proficiency in Python for scripting
- Experience in designing DSP or digital communication system datapath blocks
