The opportunity
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
What you'll do
Implement and optimize DFT architectures, including scan insertion,: compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
Set up and run Automatic Test Pattern Generation (ATPG) tools and: methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
Run and debug non-timing and SDF annotated gate-level simulations
Create and validate DFT patterns for post-silicon bringup and also help with: ATE debug through all cycles of silicon characterization
Develop test scripts, automate processes, and analyze data using programming: languages such as Perl, Python, Tcl, or C++
What they're looking for
- Bachelor’s degree in electrical engineering, computer engineering, or physics
- + years of experience in semiconductor Design For Test (DFT) engineering,: post-silicon validation, and/or production testing
- Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field
- Extensive experience in post-silicon bringup, including silicon debug,: failure analysis, and yield optimization on complex SoCs or ASICs
