The opportunity
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
What you'll do
Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using: industry standard tools like Calibre, ICV, or Pegasus
Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
Interpret and implement foundry Design Rule Manuals (DRM): translate rule updates into verified flow changes
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
Perform ESD verification: validate protection strategies, current paths, and CDM/HBM compliance
Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
What they're looking for
- Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
- Develop/modify design flows as needed to meet the overall design quality of: results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- + years of ASIC and/or physical design flow development experience in industry