The opportunity
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models.
What you'll do
Own SI/PI architecture and analysis for advanced AI ASIC packages from early: feasibility studies through production.
Develop and optimize high-speed electrical channels for 200G/400G SerDes,: PCIe, HBM, DDR, and chiplet/die-to-die interfaces.
Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers.
Define and optimize package stack-ups, transmission-line structures, via: transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI requirements.
Develop channel loss, crosstalk, impedance, skew, return-loss, and: link-budget requirements, and translate them into actionable package layout guidelines.
Perform package-level PDN analysis, including impedance, loop inductance,: DCIR, EM, dynamic voltage droop, current distribution, decoupling optimization, and power/ground architecture.
What they're looking for
- Drive die/package co-design, including bump/BGA assignment, stack-up: optimization, power/ground allocation, high-speed I/O placement, and package routing architecture.
- Develop simulation methodologies and automation flows for early architecture: exploration, design-space optimization, and repeatable SI/PI sign-off.
- + years of experience in signal integrity, power integrity, high-speed: interconnect design, PDN design and package electrical design.
- Strong understanding of signal-integrity and power-integrity fundamentals,: including transmission-line behavior, impedance, loss, crosstalk, return paths, power-distribution networks, inductance, decoupling, voltage droop, and current distribution.
