The opportunity
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
What you'll do
Responsible for evaluating design readiness for scan insertion through RTL: and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Running and evaluating scan insertion through synthesis tools and refining: scan insertion recipe for maximum coverage
Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan: chain construction and meeting basic coverage goals
Run and debug non-timing and SDF annotated gate level simulations
Creating ATPG content for use in post-silicon testing and validating that: content through gate level simulation
What they're looking for
- Collaborate with circuit physical design team, ATPG team and manufacturing: team to facilitate high quality scan coverage in silicon
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- + years of professional experience working with ASICs
- Experience in scan insertion or DFT setup
