The opportunity
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models.
What you'll do
Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
Define verification plans based on architecture and microarchitecture specs.
Develop constrained-random, directed, and system-level testbenches using: SystemVerilog/UVM or equivalent methodologies.
Build and maintain stimulus generators, checkers, monitors, and scoreboards: to ensure high coverage and correctness.
Drive bug triage, root cause analysis, and work closely with design teams on resolution.
Contribute to regression infrastructure, coverage analysis, and closure for: both block- and top-level environments.
What they're looking for
- BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.
- Proven success verifying complex IP or SoC designs in industry-standard flows
- Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).
- Strong knowledge of computer architecture concepts, memory and cache systems,: coherency, interconnects, and/or ML compute primitives.
