The opportunity
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
What you'll do
Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC: blocks and SoC integration tasks using Verilog/SystemVerilog
Optimize designs for power, performance and area
Participate in the full ASIC/FPGA design lifecycle for Starlink projects,: from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
Contribute to continual improvements to our designs by building physical and: digital tools to analyze data collected on orbit and in the lab
Engage in high-level architectural design for test systems to support: FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.
Collaborate with software engineers in developing production software for your designs
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
- + years of experience in RTL Design using SystemVerilog, Verilog or VHDL
- ASIC/FPGA system integration experience
- Proficiency in Python, C/C++, and Bash
