The opportunity
The Host and Network IO Team develops the full IO path implementation between a distributed system of server nodes, through the cluster, down to the custom RoCE network stack implemented in Cerebras' system, and over the proprietary IOs onto the WSE. As an FPGA developer on the…
What you'll do
Lead full chassis-to-wafer IO architecture and design
Improve current RTL, implement next-gen FPGA design, define future IO architectures
Produce production-ready bitstreams for deployment into large clusters running customer inference services
Work with DV team to prevent bug slips and simplify debug
Optimize bandwidth/latency over FPGA datapath and all IO interfaces
Interface with board team facilitating and executing board bringup
What they're looking for
- Drive network performance debug of large AI clusters
- Integrate leading edge networking technologies and protocols
- Lead cross-functional technical projects spanning multiple teams and: integrating diverse software and hardware components to deliver an improved network IO solution.
- Foster clear and effective communication across teams and stakeholders.
