The opportunity
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
What you'll do
Lead implementation and optimization of DFT architectures, including scan: insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
Own ATPG tools and methodologies, including generating patterns for stuck-at,: transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
Responsible for evaluating design readiness for scan insertion through RTL: and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Run and debug non-timing and SDF annotated gate level simulations
Develop test scripts, automate processes, and analyze data using programming: languages such as Perl, Python, Tcl, or C+
What they're looking for
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- + years of experience working with ASICs
- + years of experience in scan insertion and DFT setup, integration and validation
- Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
