The opportunity
Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to…
What you'll do
Define and drive formal strategy for first-pass silicon success. Own the: formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques (e.g., Bounded Model Checking, Datapath Validation, Connectivity, Sequential LEC, etc.)
Architect robust and scalable FV environments. Develop and deploy reusable: formal testbenches, methodology flows, and high-coverage SVA assertion suites for systemic deployment across multiple design blocks and projects
Technical leadership & mentorship. Serve as the team's formal Subject Matter: Expert, training and guiding logic designers and verification engineers to effectively incorporate formal methods into their workflows
Strategic planning and test plan execution. Collaborate with Architecture and: Design teams to translate complex system and IP specifications into comprehensive formal verification test plans
Drive FV Infrastructure & Reporting. Maintain and enhance continuous: integration, regression flows, and dashboarding to provide clear, actionable formal verification status and sign-off metrics to leadership
Advanced bug-hunting and debugging. Apply state-of-the-art formal techniques: (e.g., assume-guarantee, abstractions, reductions) to tackle and efficiently decompose the most challenging, intractable verification problems
What they're looking for
- BS/MS/PhD in CS/EE or related field, combined with 5+ years of hands-on: formal verification experience on shipping silicon products
- Deep, expert-level proficiency with at least one major commercial formal: verification platform (e.g., Cadence JasperGold, Synopsys VC Formal, Mentor Questa Formal)
- High level language proficiency in C++ and/or Python
- Ability to model complex designs in SystemVerilog and advanced SystemVerilog: Assertions, including writing complex cut-points and environment models for effective formal proof convergence
