The opportunity
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
What you'll do
Lead a small team responsible for the digital design of ASICs and/or FPGAs for Starshield projects.
Lead architectural trades for features, performance requirements and system: limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
Define micro-architecture, implement the RTL in Verilog/System Verilog,: integrate that in top level and deliver the fully verified, synthesis/timing clean design.
Work closely with verification team to ensure all aspects of the design are covered and verified.
Work with leaders across the engineering organization to drive product: requirements to push the performance envelope for Starshield satellites.
Recruit, develop, train, and retain world class team members who will deliver: for our Nation and amplify the team.
What they're looking for
- Provide timing constraints for those IPs and support the physical: implementation team (synthesis, timing closure, formality check).
- Participate in silicon bring-up and validation. Assist in the development of: automated test lab equipment for lab measurements.
- Bachelor’s degree in electrical engineering, computer engineering, computer: science, or another engineering discipline.
- + years of experience in RTL implementation and/or FPGA/ASIC development.