The opportunity
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models.
What you'll do
Own the microarchitecture, RTL design, and delivery of major packet-based: interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic.
Design mechanisms for routing, arbitration, ordering, flow control,: congestion management, quality of service, packet scheduling, buffering, and performance monitoring.
Develop on-chip and off-chip interfaces, protocol bridges, and custom: networking protocols or protocol extensions for scale-up and scale-out systems.
Perform substantial direct microarchitecture, SystemVerilog coding, simulation, and debug work.
Collaborate with architecture and performance teams to analyze traffic: patterns, identify bottlenecks, and optimize latency, bandwidth, fairness, and utilization under realistic workloads.
Work with verification teams to develop coverage plans, assertions, stress: scenarios, and debug strategies for highly concurrent packet and fabric behavior.
What they're looking for
- Experience designing packet-switched interconnect or networking datapaths for: AI accelerators, GPUs, CPUs, HPC systems, NICs/SmartNICs, switch ASICs, or large-scale datacenter silicon.
- Experience addressing virtualization, isolation, RAS, telemetry, security, or: memory-consistency requirements within complex networking or interconnect subsystems.
- Experience with network or NoC performance modeling, traffic simulation,: emulation, FPGA prototyping, or post-silicon traffic and performance analysis.
- Experience leading architecture or RTL delivery for first-generation: networking or interconnect IP in rapidly evolving silicon programs.
