The opportunity
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models.
What you'll do
Drive hardware/software co-design across ML research, compiler, and silicon: teams, jointly shaping kernel implementations and hardware capabilities to meet workload performance and efficiency goals.
Partner with ML research to translate model and workload needs into kernel: performance targets and compute, memory capacity, and bandwidth requirements, feeding hardware constraints and opportunities back into model and algorithm choices.
Map and optimize ML kernels for architecture, using insights from data: movement, memory hierarchy, and execution efficiency to guide both software improvements and hardware design.
Co-design support for new data structures and quantization formats across: kernels, compilers, and silicon, balancing model quality, numerical behavior, performance, power, and implementation cost.
Define and help develop specialized acceleration IP, working with compiler: and silicon partners to determine the right division of functionality across software, instructions, and dedicated hardware.
Drive ML performance modeling and simulation with the compiler team to: compare hardware/software design options, expose bottlenecks, and quantify end-to-end benefits on representative workloads.
What they're looking for
- Partner with the Silicon Architecture lead and silicon team to specify and: validate new IP, using kernel and simulation results to refine requirements and prioritize architectural improvements.
- Have deep experience with ML accelerator architecture and how compute: resources, memory systems, and data movement shape workload performance.
- Can translate model-level behavior into concrete kernel requirements and hardware design decisions.
- Have built or used accelerator performance models and simulators, and know: how to validate their assumptions and interpret their limitations.
