Senior RTL Engineer, Interconnect DesignActive$225K–$445K

Hybrid · San FranciscoCreative

The opportunity

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems…

What they're looking for

  • Partner with physical design teams to ensure interconnect structures are: implementable at target frequency, power, and area, including floorplan-aware design, pipeline strategy, timing closure, and congestion management.
  • Provide technical leadership through design reviews, architecture reviews,: documentation, mentoring, and development of reusable RTL and integration methodologies.
  • Leverage experience to help raise the bar on design work inside our team.
  • Roll up your sleeves and get your hands dirty!